Stockholm, Stockholm
Job Summary
Good understanding of ASIC/SoC life cycle Has participated in multiple ASIC/SoC verification till tapeout stage Experience writing ASIC/SoC testplans 1.Experience in ASIC/SoC Testbench definition 2.Experience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and the Universal Verification Methodology (UVM). 1.Expertise & hands-on experience in OVM/UVM methodologies using SV 2.Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans. 1. Experience in developing TB components for SOC with C, SV 1. Experience in developing TB components, including functional coverage implementation and assertion coding 2. Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic. 3.Debug complex simulation failures using waveform viewer tools to isolate design bugs from testbench issues. 4. Experince in SOC C based tests coding & debugging Experience in Gate level simulation & netlist debugging Exeprince in regression failure analayiss Functioncal and Code Coverage closure Experience in Utilizing scripting languages like Perl/Shell scripting to automate regression tests and parse large simulat
Key Responsibilities
1. Lead strategic RTL Design initiatives by architecting complex solutions with Verilog, VHDL, and SystemVerilog, ensuring alignment with enterprise goals and measurable business outcomes.
2. Establish governance and quality frameworks for RTL Design projects, utilizing advanced simulation and synthesis tools such as Synopsys Design Compiler and Cadence Genus to mitigate risk and uphold compliance.
3. Define and execute solution roadmaps that integrate emerging RTL optimization techniques, driving innovation and scalability for enterprise-wide deployments.
4. Oversee multi-disciplinary teams in delivering high-impact RTL Design solutions, mentoring senior technical staff and embedding best practices in digital design and verification.
5. Collaborate with executive stakeholders and clients to identify strategic opportunities for RTL-based differentiation, leveraging industry trends and advanced design methodologies.
6. Manage large-scale RTL programs, coordinating resource allocation and budget oversight to ensure timely, cost-effective delivery and operational risk management.
7. Integrate advanced hardware technologies and IP cores within RTL architectures to support business transformation and future-readiness.
Skill Requirements
1. RTL Design: Enterprise Strategy and Visionary Leadership in Verilog, VHDL, SystemVerilog.
2. Solid expertise in RTL synthesis, simulation, timing analysis, and optimization.
3. Advanced proficiency in EDA tools such as Synopsys Design Compiler, Cadence Genus, and Mentor Graphics Questa.
4. Excellent understanding of digital architecture, SoC integration, and hardware/software co-design.
5. Strategic knowledge of design verification, low-power design, and advanced technology nodes.
6. Strong leadership in solution governance, risk management, and quality assurance for RTL projects.
Other Requirements
1. Optional but valuable: Certified Design Engineer (CDE), Synopsys Certified Implementation Specialist, Cadence Digital Design Certification.
#body.unify div.unify-button-container .unify-apply-now: focus, #body.unify div.unify-button-container .unify-apply-#body.unify div.unify-button-container .unify-apply-now: focus, #body.unify div.unify-button-container .unify-apply-
